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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 40: PLL Specification (Cont’d)
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
PLL_F PFDMAX
PLL_F PFDMIN
Maximum Frequency at the Phase
Frequency Detector
Minimum Frequency at the Phase Frequency
Detector
550.00
19.00
500.00
19.00
450.00
19.00
450.00
19.00
450.00
19.00
MHz
MHz
PLL_T FBDELAY
Maximum Delay in the Feedback Path
3 ns Max or one CLKIN cycle
Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK
T PLLCCK_DADDR /
T PLLCKC_DADDR
T PLLCCK_DI /
T PLLCKC_DI
T PLLCCK_DEN /
T PLLCKC_DEN
T PLLCCK_DWE /
T PLLCKC_DWE
Setup and hold of D address
Setup and hold of D input
Setup and hold of D enable
Setup and hold of D write enable
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00
1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 2.40/0.00
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00
ns, Min
ns, Min
ns, Min
ns, Min
T PLLCKO_DRDY
F DCK
CLK to out of DRDY
DCLK frequency
0.65
200.00
0.72
200.00
0.99
200.00
0.99
200.00
0.70
100.00
ns, Max
MHz, Max
Notes:
1.
2.
3.
4.
5.
The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
The static offset is measured between any PLL outputs with identical phase.
Values for this parameter are available in the Clocking Wizard.
See www.xilinx.com/products/intellectual-property/clocking_wizard.htm .
Includes global clock buffer.
Calculated as F VCO /128 assuming output duty cycle is 50%.
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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